Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photodiode gate, photoconductor, or a photodiode. In a CMOS imager a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically transferred to a floating diffusion region connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photoconversion device to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the foregoing are hereby incorporated by reference herein in their entirety.
A known imager device has a pixel array with a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in an array are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for an entire array. The row lines are selectively activated by a row driver in response to a row address decoder. The column select lines are selectively activated by a column driver in response to a column address decoder. Thus, a row and column address is provided for each pixel. The imager is operated by a timing and control circuit, which controls the row and column address decoders for selecting the appropriate row and column lines for pixel readout. The control circuit also controls the row and column driver circuitry such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig), are read by a sample and hold circuit associated with the column device. A differential signal (Vrst−Vsig) is produced by a differential amplifier for each pixel which is digitized by an analog to digital converter (ADC). The analog to digital converter supplies the digitized pixel signals to an image processor which forms a digital image.
A known image sensor is depicted in cross-section in FIG. 1. A 4-transistor (4T) image sensor has a transfer transistor 56, reset transistor 57, source follower transistor (not shown) and row select transistor (not shown). The photodiode 59 shown in FIG. 1 is a conventional p-n-p photodiode having a p-type region 10 closest to the surface with an n-type region 12 aligned vertically beneath the p-type region 10. The photodiode 59 detects photon energy and generates electrons which are collected in the photodiode while the transfer gate is “OFF.” When the transfer gate is “ON,” the photon-generated electrons are transferred to the floating diffusion region 11 because of the potential difference existing between the photodiode and floating diffusion region. The electrons are then converted to voltage signals that will be read at the source follower gate.
Applicants have determined that there are two significantly high energy barriers for electrons to overcome. The barriers occur between the photodiode 59 and the floating diffusion region 11 and between the photodiode 59 and the gate of the transfer transistor 56. It becomes necessary to minimize these two energy barriers to fully utilize the generated electrons. The higher the energy barrier, the lower the output signal and responsivity in weak light intensity conditions. Image lag can also result from high energy barriers when electrons collected in the photodiode are not completely transferred before the sensor is reset.
In addition, in short gate length sensors, sub-threshold current can become significantly high because of the breakdown between n-type regions on either side of the transfer gate. In particular, the n-type region 12 of the photodiode 59 may have increased leakage problems. The depletion edge 41 in n-type region 12 is shown with a dotted line. The energy barrier between the photodiode and the transfer gate should be reduced as much as possible or eliminated in order to control leakage and maximize charges transferred from the photodiode.